1. Field of the Invention
The present invention relates to programmable logic devices (PLDs) and in particular to power management within programmable logic devices.
2. Description of the Related Art
Programmable logic devices (PLDs) are a class of integrated circuits which can be programmed by a user to implement user-defined logic functions. PLDs, long known in the art, are often used in electronic systems because, unlike custom hard-wired logic circuits or application specific integrated circuits (ASICs), PLDs can be programmed in a relatively short time and can be reprogrammed quickly to incorporate modifications to the implemented logic functions.
One major class of PLDs are referred to as programmable logic array (PLA) devices or programmable array logic (PAL) devices. Basically, these early PLDs include an AND plane which logically ANDs two or more input signals to produce product terms (P-terms), and an OR plane which logically ORs two or more of the P-terms generated by the AND plane. ("Plane" here generally refers to a grouping of logic gates known in the art and not to a geometric plane.) The AND plane is typically formed as a matrix of programmable connections where each column connects to an input pin of the PLD, and each row forms a P-term which is transmitted to the OR plane. The OR plane may be programmable (i.e., each P-term is programmably connectable to one of several different OR plane outputs), in which case the PLD is referred to as a PLA device. Alternatively, the OR plane may be fixed (i.e., each P-term is assigned to a particular OR plane output), in which case the PLD is referred to as a PAL device. The AND plane and OR plane of PLA and PAL devices implement logic functions represented in the sum-of-products form.
PLA and PAL devices were well-received by logic designers when their implemented logic functions were relatively small. However, as logic functions grew increasingly larger and more complex, logic designers were required to wire together two or more small PLDs to provide sufficient logic capacity. Although this process was tolerated during development and testing, it increased the cost and size of production units. This generated a demand for PLDs with increasingly larger logic capacity.
To meet the ever-increasing demand for greater capacity, PLDs with increasingly complex architectures have been developed. One popular complex PLD type, known as complex programmable logic devices (CPLDs), includes two or more function blocks connected together and to input/output (I/O) modules by an interconnect matrix such that each of the function blocks selectively communicates with the I/O modules and with other function blocks of the CPLD through the interconnect matrix. External pins (terminals) on the device connected to the I/O modules are also referred to as functional pins.
Each function block of the CPLD is structured like the two-level PLDs, described above. In effect, CPLDs incorporate several early PLDs and associated connection circuitry onto a single integrated circuit. This provides a circuit designer the convenience of implementing a complex logic function using a single IC.
Each function block of an early CPLD typically includes an AND array and a set of macrocells. The AND array includes a set of input lines for receiving input signals from the interconnect matrix, and a set of product term (P-term) lines for transmitting P-term signals to the macrocells. Each P-term line is connected to the input lines using programmable connections which allow logic ANDing of two or more of the input signals. Each macrocell includes an OR gate which is programmable to receive one or more of the P-term signals transmitted on the P-term lines. The OR gate of each macrocell produces a sum-of-products term which is either transmitted to the I/O modules of the CPLD, fed back through the interconnect matrix, or is transmitted on special lines to an adjacent macrocell.
Some CPLDs, such as the XC7300.TM. series CPLDs and the XC9500.TM. series CPLDs produced by Xilinx, Inc. of San Jose, Calif., incorporate "cross-point" interconnect matrices. Cross-point interconnect matrices include a plurality of parallel word (input) lines arranged perpendicular to a plurality of parallel bit (output) lines. At the intersections of the word lines and bitlines are programmable connection circuits. Each programmable connection includes a memory cell which is programmed to either connect or disconnect one word line to/from one bitline. The word lines receive signals input to the CPLD and feedback signals from the macrocells. Selected bitlines are connected to the word lines via the programmable connections to route input and feedback signals into selected function blocks. Cross-point interconnect matrices are characterized in that every word line is programmably connectable to every bitline, thereby providing the advantage of 100% routability--that is, every word line can be connected to every bitline within a cross-point interconnect matrix. Another advantage of cross-point interconnect matrices is that two or more signals on the word lines can be logically ANDed together before transmission to the function blocks. Examples of cross-point interconnect matrices are described in U.S. Pat. Nos. 5,028,821 and 5,530,378, incorporated herein by reference in their entirety.
One problem recognized in the art is that the input AND array (also referred to generally as the P-term array or simply "P-terms") in each function block consumes electric power at all times, even when the input signals are not changing. Some prior art systems used a simple power enable pin on the PLD to shut off power to the entire device when external conditions indicated that the PLD was not needed, e.g., on command or on entry of system "sleep" mode. Other prior art systems, sometimes referred to as input transition detection (ITD) systems, reduced power consumption by detecting input signal transitions (more precisely, the lack of any transitions) and removing power to the entire device when the inputs fail to change (i.e., become static) for a certain period of time.
Both of these techniques have a performance and speed penalty associated with them, however, due to the power-up and settling delay inherent in all power restoration operations. In the case of an ITD scheme, such restoration is also required whenever the inputs cease to be static: any change in the inputs necessitates determination of new outputs, and thus the PLD must be powered up.
A further drawback is the lack of design flexibility in these all-or-nothing power management schemes. In many instances, it is not desirable to turn off the entire PLD, such as when some signals are highly time sensitive or intolerant of delays. In other applications, it is not possible to route dynamic (i.e., non-static) signals away from the PLD. In the latter cases, chip-level power-down or ITD schemes cannot be used at all.
Furthermore, an important goal in programmable logic device design is ensuring that all function blocks are identical, so that there are no functional restrictions on how a designer can use each function block. In essence, each function block needs to look, behave, and perform precisely the same as every other function block so that the designer has maximum flexibility in implementing a logic design. An effective power management system (optimally) should therefore have the same impact on all function blocks. Thus, prior art systems or schemes that provide for power-down of some, but not all, function blocks are less desirable because such a device is less versatile.
Pin-locking, the ability to preserve the I/O signal assignments (or pinout) of the device from device generation to generation while preserving the same device programming and logic functionality, is also extremely important to designers. Pin-locking (compatibility) depends in part on the ability to associate any logic function with any input/output pin. Prior art systems that use dedicated power enable or ITD pins prevent designers from porting existing PLD logic designs onto new PLDs with power management and pinouts that do not match the original design. In other words, if the original logic design does not make use of a dedicated power enable or ITD pin at all, or the power enable or ITD pin is not in the same location as on the new device, then either the logic design or the circuit board layout has to be changed to accommodate a new power management scheme. Such redesign is expensive and time-consuming and thus undesirable.
A further drawback is that prior art systems often require special circuitry on the PLD. Such circuitry takes up device real estate that might otherwise be used by additional programmable logic. The use of additional "overhead" circuitry for power management thus reduces the efficiency of the PLD as compared to devices without dedicated power management circuitry.
What is needed is a method to minimize power consumption in a PLD that does not shutdown all function blocks at the same time and can remove and restore power quickly, with minimal performance degradation. In particular, what is needed is a power management scheme that allows the flexible removal of power to only those product terms in selected function blocks that do not need power all the time. Furthermore, the power management scheme must also be consistent with the PLD architectural mandates of eliminating functional restrictions differentiating any function block, product term, or macrocell from any other and preserving pin-locking compatibility. Finally, the power management scheme should utilize a minimal amount of device real estate so as to not impact the device's programmable logic capacity.